Dynamic random access memories (DRAM's) output data bits stored in their arrays through output buffers. Typically, an output buffer receives a data bit from a DRAM's array on the DRAM's internal input/output (I/O) bus. The output buffer then outputs the data bit by driving an external data bus. If the data bit is a logic "1" bit, it is desirable for the output buffer to drive the external data bus to a voltage at or near the supply voltage so the data bit will properly read as a logic "1" bit. A typical supply voltage is 3.3 volts.
A conventional output buffer 10 capable of driving an external data bus (not shown) to the supply voltage is shown in FIG. 1. Although the output buffer 10 shown in FIG. 1 is only capable of a high impedance state and a logic "1" state as described below, it will be understood that other well-known circuitry (not shown) is typically included in the output buffer 10 to make it capable of a logic "0" state as well.
During a DRAM's column address strobe precharge time t.sub.CP, the output buffer 10 is in a high impedance state. In this state, a low control signal QED* drives the output of an inverter 12 high, causing a NOR gate 14 to output a low. The low output of the NOR gate 14 drives the output of an inverter 16 high. The high output of the inverter 16 applied at the gate of an NMOS transistor 18 turns the NMOS transistor 18 on. The NMOS transistor 18 then couples the gate of an NMOS transistor 20 to ground, thereby turning off the NMOS transistor 20. As a result, a buffered data output DQ floats.
At the same time, the low output of the NOR gate 14 drives the output of an inverter 22 high. The high output of the inverter 22 applied at the gate of a PMOS transistor 24 turns the PMOS transistor 24 off, thereby isolating the NMOS transistors 18 and 20 from a first terminal 26 of a boot capacitor 28. The high output of the inverter 22 also causes an inverter 30 to output a low, thus grounding a second terminal 32 of the boot capacitor 28.
The low output of the NOR gate 14 during the high impedance state also drives the output of an inverter 34 high to a word-line voltage V.sub.WL such as 5.0 volts. Because the word-line voltage V.sub.WL is significantly greater than the supply voltage V.sub.CC, the high output of the inverter 34 applied at the gate of an NMOS transistor 36 turns on the NMOS transistor 36 and causes it to apply the full supply voltage V.sub.CC to the first terminal 26 of the boot capacitor 28. This in turn causes the boot capacitor 28 to store the supply voltage V.sub.CC during the DRAM's column address strobe precharge time t.sub.CP.
At a later time, the output buffer 10 may switch to a state in which it outputs a logic "0" bit, although a "pull down" circuit which typically drives the output of the buffer 10 to a logic "0" level is not shown in FIG. 1. In this logic "0" state, a high input signal LDQ* representing the logic "0" bit from the DRAM's array (not shown) causes the boot capacitor 28 to store the supply voltage V.sub.CC in the same way that the low control signal QED* does during the high impedance state described above.
The output buffer 10 may also switch at a later time to a state in which it outputs a logic "1" bit. In this logic "1" state, a high control signal QED* causes the inverter 12 to output a low. At the same time, a low input signal LDQ* representing the logic "1" bit from the DRAM's array (not shown) together with the low output from the inverter 12 drives the output of the NOR gate 14 high.
The high output of the NOR gate 14 causes the inverter 16 to output a low, and this low output applied at the gate of the NMOS transistor 18 turns off the NMOS transistor 18, thereby isolating the gate of the NMOS transistor 20 from ground. The high output of the NOR gate 14 also causes the inverter 34 to output a low, and this low output applied at the gate of the NMOS transistor 36 turns off the NMOS transistor 36, thereby isolating the first terminal 26 of the boot capacitor 28 from the supply voltage V.sub.CC.
At the same time, the high output of the NOR gate 14 during the logic "1" state causes the inverter 22 to output a low, thereby driving the output of the inverter 30 high. The high output of the inverter 30 drives the second terminal 32 of the boot capacitor 28 to the supply voltage V.sub.CC. Because the boot capacitor 28 stored the supply voltage V.sub.CC during the DRAM's column address strobe precharge time t.sub.CP as described above, the supply voltage V.sub.CC at the boot capacitor's second terminal 32 "boots" a boot voltage V.sub.BOOT at the boot capacitor's first terminal 26 well above the supply voltage V.sub.CC.
The low output of the inverter 22 applied at the gate of the PMOS transistor 24 turns the PMOS transistor 24 on, thereby causing it to apply the boot voltage V.sub.BOOT at the gate of the NMOS transistor 20. Because the boot voltage V.sub.BOOT is well above the supply voltage V.sub.CC, it turns the NMOS transistor 20 on and causes the NMOS transistor 20 to output a buffered signal at the DQ output at the full supply voltage V.sub.CC. The output buffer 10 then drives an external data bus (not shown) to the supply voltage V.sub.CC with the buffered signal at the DQ output. Thus, in its logic "1" state the output buffer 10 is able to drive the external data bus (not shown) to the supply voltage V.sub.CC as a result of the boot capacitor 28 storing the full supply voltage V.sub.CC previous to the logic "1" state and then generating the high boot voltage V.sub.BOOT during the logic "1" state.
Although the prior art circuit shown in FIG. 1 generally is considered satisfactory, it has been discovered that the boot capacitor 28 tends to discharge its stored voltage during operation of the output buffer 10. Generally, this has not been a problem when the output buffer 10 outputs a variety of logic "1" and "0" bits because the output buffer 10 recharges the boot capacitor 28 in its logic "0" state as described above.
This also generally has not been a problem when the output buffer 10 outputs a series of logic "1" bits, because the output buffer 10 recharges the boot capacitor 28 between the logic "1" bits during the column address strobe precharge time t.sub.CP as described above. However, current DRAM column address strobe precharge times t.sub.CP which approach 10 nS do not give the typical output buffer 10 enough time to fully recharge the boot capacitor 28 between the logic "1" bits. As a result, the boot capacitor 28 partially discharges when the output buffer 10 outputs each logic "1" bit, causing the boot voltage V.sub.BOOT to increasingly "droop" for each successive logic "1" bit. In turn, the drooping boot voltage V.sub.BOOT eventually causes the NMOS transistor 20 to output the buffered signal DQ at less than the full supply voltage V.sub.CC. Unfortunately, this may cause some of the logic "1" bits to be misread as logic "0" bits.
Therefore, there is a need in the art for an output buffer which can consistently output a series of logic "1" bits at a voltage near the supply voltage.